FIELD OF THE INVENTION
The invention relates to a semiconductor component and to processes for its fabrication. The invention relates in particular to a semiconductor component with a gate dielectric of a field-effect transistor and/or with a storage node dielectric in a memory cell.
In order to maintain or increase international competitiveness, it is necessary to continually reduce the costs that have to be expended to realize a specific electronic function, and thus to continuously increase productivity. The guarantor for increasing productivity in recent years has been and remains CMOS technology or DRAM technology. These two technologies have been able to increase productivity by progressive miniaturization.
However, the progressive miniaturization of MOS transistors entails the necessity of using ever thinner dielectric layers as gate dielectrics for effective driving of the transistors. If, as is generally customary nowadays, silicon dioxide is used as the gate dielectric, then the layer thickness of the gate dielectric in 0.1 μm technology would have to be less than 1.5 nm. However, it is very difficult to produce such thin silicon dioxide layers reproducibly with sufficient accuracy. Deviations of just 0.1 nm mean fluctuations in the layer thickness of the order of magnitude of 10%. Furthermore, in the case of such thin silicon dioxide layers, high leakage currents arise through the silicon dioxide layer, since, through the quantum mechanical tunnel effect, the charge carriers can surmount the potential barrier produced by the silicon dioxide layer.
In the development of large-scale integrated memory components, the cell capacitance of an individual memory cell must be maintained or even improved despite progressive miniaturization. In order to achieve this aim, ever thinner dielectric layers, usually silicon oxide or oxide-nitride-oxide layers (ONO), and folded capacitor electrodes (trench cell, stack cell) are also being used. However, the reduction in the thickness of the storage dielectric leads to a considerable increase in the leakage currents (tunneling currents) through the dielectric. It has been proposed, therefore, to replace the customary silicon dioxide layers or oxide-nitride-oxide layers by materials having a higher relative dielectric constant (∈r). With such a material, comparatively thick layers of more than 5 nm can be used as the gate dielectric or the storage dielectric, which, however, correspond electrically to a silicon dioxide layer of distinctly smaller than 5 nm. The thickness of such a layer is easier to control and the tunneling current through the layer is distinctly reduced.
By way of example, titanium oxide or tantalum pentoxide or layer stacks of oxide/titanium oxide or oxide/tantalum pentoxide have been proposed as materials for the gate dielectric. By way of example, barium strontium titanate (BST, (Ba,Sr)TiO3), lead zirconate titanate (PZT, Pb(Zr,Ti)O3) or lanthanum-doped lead zirconate titanate or strontium bismuth tantalate (SBT, SiBi2Ta2O9) are used as materials for the storage dielectric.
Unfortunately, these materials have a number of drawbacks for their new uses. For example, it is customary to use chemical vapor deposition (CVD) processes for the fabrication of a gate dielectric from titanium oxide or tantalum pentoxide.
However, the layers fabricated in this way have impurities that are attributable to the process gases used in the CVD processes. These impurities lead to charges and traps in the layers, which in turn have an adverse effect on the operation of the transistor. Moreover, these layers or layer stacks generally do not produce a sufficient increase in the dielectric constant (∈r).
With the new materials which are used as storage dielectrics, it has been found that they belong to the group of materials which cannot be etched or can only be etched with difficulty by chemical methods, in which materials the etching abrasion, even when using “reactive” gases, is based primarily or almost exclusively on the physical part of the etching. On account of the small or absent chemical component of the etching, the etching abrasion of the layer to be structured is of the same order of magnitude as the etching abrasion from the mask or the base layer (etching stop layer), i.e. the etching selectivity with respect to the etching mask or base layer is generally low (between approximately 0.3 and 3.0). Consequently, the erosion of the masks with inclined flanks and the inevitable facet formation (beveling, tapering) on the masks results in that only a low dimensional accuracy of the structuring can be ensured. Therefore, this faceting restricts the smallest structure sizes that can be achieved during the structuring and the steepness of the profile flanks that can be achieved in the layers that are to be structured.
Furthermore, complicated and expensive deposition processes and barrier layers which are difficult to process, such as platinum or ruthenium, are necessary for the fabrication of BST, PZT or SBT layers. Moreover, on account of lack of thermal stability, BST layers cannot be used for deep trench capacitors.